华为提出了“τ缩放”和“LogicFolding”两种新方法，旨在不依赖最先进光刻工具的前提下，缩小与台积电的性能差距。其核心思想是将衡量芯片进步的指标从晶体管尺寸转向信号传输延迟（τ）。LogicFolding作为具体实现，通过垂直堆叠逻辑电路层并采用混合键合，将需要通信的电路紧邻放置，从而缩短关键线路、降低电阻和寄生电电容，提升信号速度。华为表示，其下一代麒麟手机芯片将是对τ缩放规律的首次全面测试。
🇨🇳 Huawei just released breakthrough chip design approach "LogicFolding" that will close it's gap with TSMC.
The technical paper behind it.
The core idea is that chips should stop measuring progress mainly by how small transistors are and start measuring progress by how much time delay can be removed from the whole machine.
A chip wastes time when signals move through long wires, memory paths, chip-to-chip links, and software communication layers, so Huawei calls this delay τ, or tau.
Huawei’s paper introducing "LogicFolding" says the next chip breakthrough may come from cutting wasted time inside the machine.
That is what "τ scaling" means.
τ is the delay that accumulates before useful computing happens: a transistor switches, a signal crosses a wire, data reaches memory, a chip talks to another chip, or a server waits for a response.
Moore’s Law reduced this delay indirectly because shrinking transistors also shortened many of the paths around them.
But modern chips are no longer slowed only by transistor size.
They are slowed by wire resistance, parasitic capacitance, clock skew, memory distance, protocol conversion, chip-to-chip communication, and the cost of moving data.
So τ scaling changes the question from “how small is the transistor?” to “where is time being lost?”
LogicFolding is Huawei’s physical answer to that question inside a chip.
In a normal chip, related logic gates are spread across a flat surface, so signals often travel sideways through long metal routes before reaching the next important gate.
Those wires behave like sticky pipes: resistance slows current, capacitance must be charged and discharged, and every extra distance creates delay and wastes energy.
LogicFolding tries to stack active circuit layers vertically and connect them with very fine hybrid bonds, so circuits that need to talk are placed above and below each other instead of far apart on one plane.
The signal now takes a shorter route, the critical path becomes faster, clock timing becomes cleaner, and the same manufacturing node can deliver more performance.
Huawei is trying to win not by making every switch smaller, but by making every important signal travel less, wait less, and arrive sooner.
🇨🇳 Huawei reveals a new chip design breakthrough under US sanctions pressure. A design approach meant to close the gap with TSMC and Intel without relying only on smaller transistors, by making chip signals travel less distance. They want 1.4nm-class density without owning the world’s best lithography tools i.e. they are trying to replace Moore’s Law with Tau Scaling Law. To note, Huawei has been blocked from normal access to TSMC since the US tightened foreign direct product rules around Huawei in 2020, and TSMC later said it had not supplied Huawei since mid-September 2020. Proposed τ Scaling as a new way to make chips faster when shrinking transistors is no longer delivering the same gains. Said its next Kirin phone chip will be the first full test of Tau Scaling Law, Old chip progress mostly came from making every transistor smaller, but Huawei’s idea shifts the target from smaller geometry to shorter signal delay, meaning less time wasted while electrical signals crawl through wires, gates, memory paths, and system links. LogicFolding attacks the circuit layout itself by folding logic blocks closer together, shortening critical wires, reducing resistance and parasitic capacitance, and letting signals switch faster with denser placement. So LogicFolding is the circuit-level piece: it tries to place related logic closer together, shorten key wires, cut electrical drag from resistance and parasitic capacitance, and raise performance without needing a full manufacturing-node leap. Huawei is also pushing the same timing idea across the full stack: transistors, circuits, chip architecture, software scheduling, and system interconnects all get tuned to reduce τ, the delay constant that limits speed and efficiency. The bold claim is that Huawei has already mass-produced 381 chips using this thinking, and future high-end chips could reach density comparable to 14Å, or 1.4nm, without relying only on classic process shrinkage. Says this path could reach 1.4nm-class, or 14Å-class, density by 2031, while TSMC and Intel target similar physical nodes around 2029. Huawei calls it Her’s Law, after He Tingbo, the chip leader who helped turn HiSilicon into Huawei’s survival engine after US export controls. --- huawei. com/en/news/2026/5/ieee-iscas-tau-scaling在 X 查看被引用的帖子
来源：Rohan Paul · x.com