HPC-Ops 是一个面向 LLM 推理的开源算子库,已部署于腾讯的大规模生产服务中。其核心算子,包括 Dynamic Attention 和 Fused MoE,在混元的在线推理中发挥着关键作用,将 Hy3 模型的 TPOT 最多降低 48.8%。HPC-Ops Attention、Router GEMM 和 MoE 现已集成到 SGLang 的主分支中,将这些经过生产验证的优化带给开源服务社区。
在这篇博客中,我们介绍 HPC-Ops 中三个重要算子的设计及其与 SGLang 的集成。随后,我们展示在 H20 上的算子基准测试和服务结果,以及 H200 的验证结果。这些集成面向 NVIDIA Hopper GPU(SM90),并已在 Qwen3、Hy3 和 LongCat 工作负载上完成验证。
亮点
- Attention:在 H20 上,HPC-Ops 动态调度相比其静态 split-KV 调度达到 2.95×,并且在每个测量用例中平均比 FlashInfer 和 FlashAttention 中的最优者快 2.25×。在上游 H200 验证中,集成 Hy3-FP8 路径并搭配 FP8 KV cache,相比 FlashAttention 将输出吞吐量提升 3.7–5.9%。
- Router GEMM:在 H20 上,HPC-Ops 比 FP32 cuBLAS 快 1.30–3.22 倍,而其相对于 FP32 cuBLAS 的最大绝对误差为 0.00177,相比之下 TF32 cuBLAS 为 0.06464。在上游 H200 LongCat-Flash 内核验证中,它相比现有 FP32 路径实现了 4.31 倍加速。
- MoE:在 H20 上,HPC-Ops 在 Hy3 上相比 SGLang 和 vLLM 基线中的最优者,实现了每批次平均加速 TP8 / EP1 下 1.08 倍和 TP1 / EP8 下 1.21 倍。在上游 Qwen3/H200 内核基准测试中,它在八个 token 时相比 Triton 最高达到 4.21 倍。
- 端到端服务:在 8× H20 搭配 Hy3-FP8 上,同时启用 HPC-Ops Attention 和 MoE 使 TPOT 在批次大小 4–64 时降低 15.1–48.8%,TTFT 在批次大小 4–16 时降低 3.3–6.0%。在 8× H20 搭配 LongCat-Flash-Lite-FP8 上,启用 HPC-Ops Router GEMM 使输入吞吐量在批次大小 4–64 时提升 5.5–6.1%。
注意力、路由与专家:MoE 模型服务中的三条热点路径
生产环境中的 MoE 服务很少像孤立内核基准测试中所测量的那样呈现均匀负载。它在同一条对延迟敏感的路径中,融合了变长 Attention 计算、对精度敏感的路由,以及稀疏专家执行;长上下文、多轮对话和智能体工作负载进一步拉大了活跃 KV 长度的分布范围。因此,服务性能不仅取决于原始的矩阵乘法吞吐量,还取决于负载均衡、数值保真度和开销控制。
这些约束在 MoE 模型服务的三个性能关键阶段中显现出来。在 decode 阶段,Attention 计算随每个请求的活跃 KV 长度而扩展,使变长批次成为一个负载均衡问题。Router GEMM 生成用于 top-k 选择的分数,其中微小的数值变化就可能改变专家的选择。随后,被选中的专家处理小而参差不齐的 token 组,使得元数据构建、token 搬运、中间存储和启动开销足以与专家 GEMM 本身相匹敌。
HPC-Ops 为每个阶段提供了专用算子来应对:针对 Attention 的负载感知调度、针对 Router GEMM 的精度感知公式,以及针对 MoE 的融合流水线,后者消除了独立的 gather 操作并减少了启动和中间流量。上游集成通过 SGLang 的原生后端和 dispatch 接口,将这些算子与 SGLang 的服务运行时配对。以下各节将解释每个算子的设计方式。
Attention:变长 decode 的负载均衡
在解码阶段,每个新 token 都要对请求的完整 KV cache 做注意力计算,因此 Attention 的工作量会随活跃序列长度而增长。一个缓存了 16K token 的请求,其 KV 计算量大约是缓存 1K token 请求的 16 倍。在生产环境中,提示词和输出长度差异极大,而连续批处理会把处于不同生成阶段的请求放进同一次 launch;因此一个批次里常常既有很短的 KV cache,也有长达数万 token 的序列。
静态 split-KV 调度会把工作映射到一个固定的 launch grid 上,覆盖 KV heads、请求和 KV chunks,并且整个批次共用同一套划分策略。静态 split-KV 调度器通常遵循两种策略之一,而这两种策略在混合长度批次上表现都不好。(
1) 固定 split 数量,长请求就会产生重得多的 chunks:短请求的 CTA 早早完成,而少数长时间运行的 CTA 决定了 kernel 的尾部延迟。(2) 改为固定 chunk 大小,那么 grid 就必须为最长的请求预留足够多的 splits,导致较短的请求留下空 chunk 或几乎为空的 chunk,却仍然占用调度槽位。
一种策略造成工作量不均;另一种则调度了根本不存在的工作。
围绕活跃 KV 工作进行调度
HPC-Ops 用一个持久化 kernel 取代了静态的按请求拆分方式,该 kernel 会根据批次的实际长度分布,在多个 CTA 之间动态平衡 KV tile。对于每个 decode 批次,一个 assign kernel 会根据实时的 KV 长度构建全局任务映射:它将每个序列切分为统一的 64-token tile,汇总所有 head 和请求的 tile 数量,再将总数除以持久化 CTA 的数量,从而设定每个 CTA 的 tile 预算。
分配 kernel 会为每个 CTA 的 bin 填充至该预算,然后再溢出到下一个 bin,因此长序列会按其长度比例跨越多个 CTA,而短序列只贡献其实际拥有的 tile。最小工作量下限可防止在总工作量较小时出现过度分区,从而使下游的 combine 保持低成本。
任务映射在每个 decode 步骤中根据设备端序列长度生成一次,并在各 Transformer 层之间复用,从而摊薄其开销。
在执行时,每个 CTA 会清空其分配的 bin。对于每个描述符,它会对一个或多个连续的 KV tile 计算 Attention,并写入带有其 log-sum-exp 统计量的部分输出;同一个常驻 CTA 会继续处理下一个描述符,直到其 bin 为空。
由于每个 CTA 只为给定请求生成部分结果的一个子集,因此一个最终的 combine kernel 会读取每个请求和 head 的实际 chunk 数量,并在正确的全局 softmax 归一化下合并这些部分结果。近乎相等的 bin 大小确保各 CTA 大致同时完成,从而消除了少数异常长的请求否则会造成的 kernel 尾部。
融合式 attention 前导
对于 Hy3 FP8,HPC-Ops 将 Attention 前导部分融合到 QKV 投影之后:它在 RoPE 之前应用 QK-Norm,以逐 token、逐 head 的缩放因子输出 FP8 格式的 Q,并将 K 和 V 直接写入分页 FP8 缓存。
它将量化后的 Q 及其缩放因子直接传递给主 Attention kernel,避免了重新量化。该融合路径消除了中间张量及其相关的 HBM 往返,并在 prefill 和 decode 中省去了单独的 kernel 启动。
Router GEMM:平衡路由精度与吞吐量
Router 精度直接影响 MoE 模型质量。在每个 MoE 层,router 将隐藏状态投影为专家分数,对这些分数进行 top-k 选择来决定哪些专家执行。第 k 个和第 (k+1) 个专家之间的分数差异可能很小,因此该投影的算术精度决定了是否能选出正确的专家。
为保持 router 精度,一些生产模型即使隐藏状态为 BF16,仍保留 FP32 的 router 权重。将这些权重转换为 BF16 可以获得 BF16 Tensor Core 的吞吐量,但会丢弃可能翻转 top-k 决策的低位尾数位。完整的 FP32 GEMM 保留所有权重精度,但 Tensor Core 吞吐量较低。
一种精度感知的 BF16 方案
HPC-Ops 通过将 FP32 权重分解为两个 BF16 分量来解决这一问题。它通过直接截断提取出一个 BF16 高位部分 ,然后从缩放后的残差中构造出第二个 BF16 分量 。原始权重被近似为 ,因此矩阵乘积变为两次 BF16 GEMM,其结果通过一个缩放校正进行合并,以恢复低阶尾数贡献。单个 kernel 执行两次 BF16 乘法:它从共享内存中一次性加载激活 tile,在 FP32 寄存器中累加两个部分结果,在 epilogue 中应用 缩放,并将最终的 FP32 router 分数写入全局内存。这种公式化方法在 BF16 Tensor Core 上执行主要算术运算的同时,恢复了接近完整 FP32 GEMM 的精度。
在框架层面,SGLang 在模型加载时缓存分解后的权重对,并在请求和 CUDA graph 重放之间复用。形状感知调度在实测的交叉点上选择使用 HPC-Ops kernel 还是默认路径。低于这些交叉点时,单一 FP32 路径更快,因为两次乘积的开销超过了 Tensor Core 带来的收益。
MoE:减少小型专家 GEMM 周边的开销
在 decode 阶段,MoE 层中的每个专家只接收少量 token。由此产生的专家 GEMM 规模小且受内存带宽限制,GPU 的 SM 在这些形状下利用率不足。负载不均衡进一步加剧了这一问题:路由到每个专家的 token 数量因专家而异,并且逐步变化,使得难以将这些小而 uneven 的 tile 均匀分配到可用的 SM 上。
除了专家 GEMM 本身之外,围绕它们进行的各项操作也带来了可观的开销。传统的 MoE 路径将多个独立 kernel 串联起来:路由、将 token 收集到各专家缓冲区、Gate-Up GEMM、激活与量化、Down GEMM,以及将 top-k 加权结果归约回 token 位置。
收集步骤在任何 matmul 开始之前,就已在 HBM 中物化出一个完整的 token 张量,而后续每个阶段都要为中间结果付出各自的 kernel 启动和 HBM 往返开销。当 GEMM 规模较小时,这些周边开销在该阶段墙钟时间中占据了与之相当的比例。
面向延迟的融合式 MoE 流水线
针对低批量推理,HPC-Ops MoE 后端将路由与索引预处理、Gate-Up、激活与重量化、Down,以及 top-k 加权归约协调在一条低延迟流水线中,该流水线围绕任务映射驱动的持久化专家 GEMM 构建。
- 路由与索引构建。从选定的 top-k 专家 ID 出发,一次共享内存计数遍历将 token–专家分配组织为按专家划分的连续输出区间,从而减轻全局原子操作压力,并构建出持久化专家 GEMM 直接消费的路由索引和逐 tile 任务映射。
- Gate-Up 与激活。Gate-Up GEMM 通过路由索引直接读取原始 token,跳过了独立的收集步骤及其额外的 HBM 流量。随后,SiLU-and-mul 与 FP8 重量化作为一个融合 kernel 运行,其输出由 Down GEMM 直接读取。
- 占用优先,不做 warp 特化。 单个 warp 组同时处理数据搬运和矩阵运算,而不是划分出独立的生产者组和消费者组。这提高了 CTA 驻留率,并将内存延迟隐藏从 CTA 内部的软件流水线转移到跨 CTA 的硬件调度。持久化网格随后消费这些任务映射,将细小且不均匀的专家 tile 分散到各个 SM 上。
- PDL 链式阶段。 程序化依赖启动(Programmatic Dependent Launch)将每个下游 kernel 的启动与前一个阶段的尾部重叠,减少了 Gate-Up、激活、Down 以及最终的 top-k 加权归约之间的间隙,后者将专家输出恢复为 token 顺序。
这些优化共同减少了关键路径上的中间流量和 kernel 启动开销。
从 HPC-Ops kernel 到 SGLang
通过 SGLang 的原生后端和调度接口,HPC-Ops 直接作用于服务运行时已有的状态,同时保持为一个独立维护的算子库。Attention 消费分页 KV 存储和实时的设备端序列元数据,无需额外的布局转换;Router GEMM 在跨请求和 CUDA graph 重放中复用预处理权重和工作区;MoE 遵循 SGLang 的专家 ID 和分区,无需额外重映射。
这些集成在保持每个算子预期数据路径的同时,契合了 SGLang 现有的执行模型。
三条集成的算子路径总结如下:
| HPC-Ops 算子 | 优化目标 | 精度 | 上游 PR |
|---|---|---|---|
| 注意力 | 负载均衡的混合长度解码,以及融合的 QK-Norm、RoPE、量化和 KV 写入前导 | BF16 激活;BF16 或 FP8 E4M3 KV cache | #30540、#32304 |
| 路由器 GEMM | 精度感知的路由器投影,使用 BF16 Tensor Core,同时保留 FP32 权重信息 | BF16 激活 × FP32 权重 → FP32 分数 | #30247、#31943 |
| MoE | 围绕小型且不均匀的专家 GEMM 的低开销执行 | BF16 隐藏状态;FP8 E4M3 专家权重 | #30541 |
快速开始
本指南介绍如何在 SGLang 中使用 HPC-Ops 的 Attention、Router GEMM 和 MoE 算子。
安装
从源码安装 HPC-Ops:
git clone https://github.com/Tencent/hpc-ops.git
cd hpc-ops
make wheel
python3 -m pip install dist/*.whl
HPC-Ops 已包含在 SGLang 官方的 x86_64 开发镜像中(lmsysorg/sglang:dev,或针对 CUDA 12.9 的 lmsysorg/sglang:dev-cu12),因此使用这些镜像时无需单独安装。
Attention 与 MoE
Attention 和 MoE 在 SGLang 中是相互独立的后端选择,可以分别启用,也可以针对兼容的模型(如 Qwen3 和 Hy3)同时启用。以下示例同时选择了两个 HPC-Ops 后端,并启用了 FP8 KV-cache 的 Attention 路径:
python3 -m sglang.launch_server \
--model tencent/Hy3-FP8 \
--tp-size 8 \
--attention-backend hpc_ops \
--kv-cache-dtype fp8_e4m3 \
--page-size 64 \
--moe-runner-backend hpc_ops
对于 BF16 KV cache,请省略 --kv-cache-dtype fp8_e4m3。若只想使用其中一个 HPC-Ops 算子,只需指定对应的后端选项。
Router GEMM
在 SGLang 中,HPC-Ops Router GEMM 在执行 BF16 Tensor Core 矩阵运算的同时,保留了 FP32 router 权重的低阶信息。该集成路径已在 LongCat-Flash Chat 和 Lite 上完成验证,并会在支持的模型和 router 形状下自动选用。安装 HPC-Ops 后,标准的 LongCat-Flash 启动即可使用它:
python3 -m sglang.launch_server \
--model meituan-longcat/LongCat-Flash-Lite-FP8
性能评估
HPC-Ops 后端目前支持 NVIDIA Hopper 架构 GPU,并在 H20 上实现最佳性能。以下评估涵盖 H20 上的算子基准测试、8× H20 上的端到端 SGLang 服务,以及上游 SGLang pull request 中报告的 H200 结果。
H20 算子基准测试
Attention。
Attention 调度器最显著的收益体现在混合长度 decode 场景中,此时同一批次内的请求可能具有差异极大的 KV-cache 长度。我们评估了从均匀分布到高度偏斜分布的 FP8 KV-cache decode;表中 A×B 表示 A 个 KV 长度为 B 的请求。为隔离调度效果,我们将 HPC-Ops 动态调度与其静态 split-KV 对应方案进行对比,同时以 FlashInfer 和 FlashAttention 作为额外基线。动态调度相对静态调度的增益随偏斜程度增大而增长,从均匀 64×0.5K 批次上的持平,到 1×128K + 31×4K 混合场景下的 2.95×。在所有六个案例中,动态调度平均比各案例中 FlashInfer 和 FlashAttention 的最优者快 2.25×。
表 1:H20 上不同 KV 长度分布下的解码延迟。越低越好。
| 解码场景 | HPC-Ops 动态 | HPC-Ops 静态 | FlashInfer | FlashAttention | 动态 vs. 静态 |
|---|---|---|---|---|---|
| 64×0.5K | 0.013 ms | 0.013 ms | 0.050 ms | 0.025 ms | 1.00× |
| 64×4K | 0.033 ms | 0.043 ms | 0.221 ms | 0.095 ms | 1.32× |
| 32×0.125K + 32×4K | 0.020 ms | 0.033 ms | 0.119 ms | 0.053 ms | 1.59× |
| 2×32K + 30×4K | 0.032 ms | 0.056 ms | 0.169 ms | 0.094 ms | 1.76× |
| 1×64K + 15×4K | 0.042 ms | 0.097 ms | 0.118 ms | 0.065 ms | 2.32× |
| 1×128K + 31×4K | 0.063 ms | 0.186 ms | 0.220 ms | 0.097 ms | 2.95× |

图 1:随着实时 KV 工作负载愈发不均衡,动态调度变得越来越有效。越低越好。
Router GEMM。
我们首先用通用的 sweep 来评估 Router GEMM。在所测量的 M 值范围内,HPC-Ops 比 FP32 cuBLAS 快 1.30–3.22×,比 TF32 cuBLAS 快 1.25–1.78×。以 FP32 cuBLAS 作为数值参考,最大绝对误差保持在 0.00177 或以下,而 TF32 为 0.06464。
表 2:在 H20 上 K = 4096、N = 192 时的 BF16 × FP32 Router GEMM 延迟。越低越好。
| M | HPC-Ops | FP32 cuBLAS | TF32 cuBLAS | 相比 FP32 的加速比 | 相比 TF32 的加速比 |
|---|---|---|---|---|---|
| 1 | 11.200 µs | 14.576 µs | 14.048 µs | 1.30× | 1.25× |
| 16 | 11.744 µs | 23.808 µs | 18.752 µs | 2.03× | 1.60× |
| 48 | 12.144 µs | 31.008 µs | 20.064 µs | 2.55× | 1.65× |
| 96 | 13.904 µs | 31.760 µs | 24.720 µs | 2.28× | 1.78× |
| 208 | 17.088 µs | 39.280 µs | 28.928 µs | 2.30× | 1.69× |
| 512 | 26.992 µs | 86.976 µs | 44.736 µs | 3.22× | 1.66× |
| 1024 | 50.640 µs | 110.480 µs | 68.544 µs | 2.18× | 1.35× |
| 2048 | 76.688 µs | 198.576 µs | 100.800 µs | 2.59× | 1.31× |
| 4096 | 141.120 µs | 403.728 µs | 205.760 µs | 2.86× | 1.46× |

图 2:Router GEMM 相对于 FP32 cuBLAS 的数值误差(左)以及相对于 FP32 和 TF32 cuBLAS 的延迟(右)。越低越好。
随后我们重新测试了 LongCat-Flash 所使用的两种 router 形状。在 SGLang 的模型感知调度范围内,相较于 SGLang 默认实现,HPC-Ops 为 Chat 形状带来 1.06–2.83× 的加速,为 Lite 形状带来 1.09–2.46× 的加速。
表 3:在 H20 上,LongCat-Flash Router GEMM 在 SGLang 调度范围内的延迟。越低越好。
| M | Chat 默认 | Chat HPC-Ops | 加速比 | Lite 默认 | Lite HPC-Ops | 加速比 |
|---|---|---|---|---|---|---|
| 64 | 39.19 µs | 37.01 µs | 1.06× | — | — | — |
| 128 | 74.18 µs | 59.36 µs | 1.25× | 25.83 µs | 23.72 µs | 1.09× |
| 256 | 100.03 µs | 82.47 µs | 1.21× | 41.87 µs | 34.01 µs | 1.23× |
| 512 | 190.37 µs | 141.73 µs | 1.34× | 71.89 µs | 41.95 µs | 1.71× |
| 1024 | 380.68 µs | 207.00 µs | 1.84× | 108.64 µs | 74.09 µs | 1.47× |
| 2048 | 961.15 µs | 339.04 µs | 2.83× | 235.81 µs | 106.81 µs | 2.21× |
| 4096 | 1469.70 µs | 670.14 µs | 2.19× | 423.52 µs | 172.44 µs | 2.46× |
| 8192 | 2881.00 µs | 1333.84 µs | 2.16× | 835.22 µs | 339.66 µs | 2.46× |

图 3:在 SGLang 的 dispatch 范围内,LongCat-Flash Chat(左)与 Lite(右)形状下的 Router GEMM 延迟。越低越好。
MoE。
对于 MoE,我们在 Hy3 形状下以 TP8 / EP1 和 TP1 / EP8 配置对完整融合算子进行基准测试,并与 SGLang、vLLM Triton 和 vLLM CUTLASS 进行对比。取每一行三个基线中的最低延迟,HPC-Ops 在 TP8 / EP1 下实现了 1.08× 的平均每批次加速,在 TP1 / EP8 下实现了 1.21× 的平均每批次加速,在低延迟解码中常见的中小批次规模下增益最大。
表 4:H20 上 TP8 / EP1 配置下的 Hy3 MoE 延迟。越低越好。
| 批次 | HPC-Ops | SGLang | vLLM Triton | vLLM CUTLASS | 相对最优的加速比 |
|---|---|---|---|---|---|
| 16 | 85.7 µs | 88.6 µs | 124.2 µs | 209.2 µs | 1.03× |
| 32 | 124.0 µs | 137.2 µs | 184.3 µs | 275.6 µs | 1.11× |
| 64 | 147.2 µs | 164.4 µs | 374.9 µs | 330.3 µs | 1.12× |
| 128 | 161.5 µs | 179.9 µs | 302.9 µs | 345.3 µs | 1.11× |
| 256 | 170.1 µs | 191.5 µs | 310.9 µs | 351.6 µs | 1.13× |
| 512 | 194.5 µs | 230.1 µs | 331.6 µs | 369.2 µs | 1.18× |
| 1024 | 281.4 µs | 300.5 µs | 652.7 µs | 438.3 µs | 1.07× |
| 2048 | 491.8 µs | 522.5 µs | 731.5 µs | 794.4 µs | 1.06× |
| 4096 | 872.0 µs | 899.2 µs | 1366.0 µs | 1230.7 µs | 1.03× |
| 8192 | 1695.0 µs | 1712.7 µs | 2216.8 µs | 2362.9 µs | 1.01× |
| 16384 | 3241.9 µs | 3257.1 µs | 4329.1 µs | 4364.4 µs | 1.00× |
表 5:Hy3 MoE 在 H20 上 TP1 / EP8 配置下的延迟。越低越好。
| Batch | HPC-Ops | SGLang | vLLM Triton | vLLM CUTLASS | 相对最优方案的加速比 |
|---|---|---|---|---|---|
| 4 | 118.6 µs | 183.1 µs | 147.4 µs | 140.4 µs | 1.18× |
| 8 | 136.7 µs | 231.5 µs | 192.8 µs | 170.7 µs | 1.25× |
| 16 | 149.8 µs | 234.2 µs | 198.4 µs | 263.5 µs | 1.32× |
| 32 | 153.6 µs | 475.3 µs | 214.6 µs | 264.4 µs | 1.40× |
| 64 | 166.5 µs | 477.3 µs | 358.1 µs | 266.8 µs | 1.60× |
| 128 | 213.5 µs | 482.3 µs | 251.7 µs | 272.6 µs | 1.18× |
| 256 | 386.2 µs | 494.3 µs | 454.9 µs | 493.5 µs | 1.18× |
| 512 | 705.5 µs | 970.7 µs | 691.7 µs | 741.7 µs | 0.98× |
| 1024 | 1342.6 µs | 1476.8 µs | 1369.1 µs | 1359.1 µs | 1.01× |
| 2048 | 2513.9 µs | 2871.2 µs | 2668.7 µs | 2530.4 µs | 1.01× |

图 4:Hy3 MoE 在 TP8 / EP1 与 TP1 / EP8 配置下的延迟。越低越好。
H200 算子验证
上游 PR 还包含 H200 服务结果,证实性能提升在 Hopper GPU 上具有普适性。
表 6:上游 SGLang pull request 中报告的算子验证。
| 算子 | 上游验证工作负载 | 对比 | 结果 |
|---|---|---|---|
| FP8 注意力 | Hy3-FP8 搭配 FP8 KV cache;混合长度解码 | HPC-Ops 动态调度 vs. HPC-Ops 静态 split-KV | 输出吞吐量 +2.0%;总吞吐量 +2.0%;TTFT 中位数 −5.3% |
| BF16 注意力 | Qwen3 搭配 BF16 KV cache;混合长度解码 | HPC-Ops 动态调度 vs. HPC-Ops 静态 split-KV | 输出吞吐量 +3.0%;平均 E2E 延迟 −2.8%;平均 TPOT −2.8% |
| Router GEMM | LongCat-Flash Chat 与 Lite 的 router 形状 | HPC-Ops Router GEMM vs. SGLang 默认实现 | Kernel 加速比:1.56–4.31× |
| MoE | Qwen3 FP8 MoE 负载,从 1 到 4,096 tokens | HPC-Ops MoE 对比 SGLang Triton 融合专家 | 内核加速:0.89–4.21× |
端到端性能
端到端评估在 8× NVIDIA H20 GPU 上运行,对照相应的默认 SGLang 实现。在 Hy3-FP8 上,采用 TP8 与 FP8 KV cache,我们通过同时启用 HPC-Ops Attention 和 MoE 来测量综合服务影响。在 LongCat-Flash-Lite-FP8 上,仅测量 Router GEMM。我们还汇总了上游 SGLang pull request 中报告的 H200 服务验证结果。
Hy3-FP8:Attention 与 MoE。
在 8K 输入和 4K 输出下,HPC-Ops 在 batch size 1 时将 TPOT 降低 3.3%。在 batch size 4–64 范围内,降幅增至 15.1–48.8%。
表 7:启用 FP8 KV cache 以及 HPC-Ops Attention 和 MoE 后的 Hy3-FP8 TPOT。越低越好。
| Batch | SGLang 默认 | HPC-Ops | 提升 |
|---|---|---|---|
| 1 | 7.56 ms | 7.31 ms | 3.3% |
| 4 | 11.10 ms | 9.42 ms | 15.1% |
| 8 | 14.29 ms | 10.76 ms | 24.7% |
| 16 | 22.90 ms | 13.09 ms | 42.8% |
| 32 | 35.33 ms | 18.09 ms | 48.8% |
| 64 | 40.70 ms | 23.81 ms | 41.5% |
在 8K 输入下,HPC-Ops 在 batch size 1–16 范围内将 TTFT 改善了 3.3–9.0%。
表 8:Hy3-FP8 在 8K 输入下使用 FP8 KV cache 的 TTFT。正向改善意味着延迟更低。
| Batch | SGLang 默认 | HPC-Ops | 改善 |
|---|---|---|---|
| 1 | 460.67 ms | 419.43 ms | 9.0% |
| 4 | 1612.47 ms | 1533.66 ms | 4.9% |
| 8 | 3210.93 ms | 3018.68 ms | 6.0% |
| 16 | 5810.53 ms | 5619.48 ms | 3.3% |
在 batch size 为 16 时,我们还在禁用 chunked prefill 和 prefix caching 的情况下,将输入长度从 2K 扫描到 8K。HPC-Ops 在三种输入长度下将 TTFT 提升了 2.3–8.9%。
表 9:在 batch size 为 16 时,使用 FP8 KV cache 的 Hy3-FP8 TTFT 在不同输入长度下的表现。正向提升表示延迟降低。
| 输入长度 | SGLang 默认 | HPC-Ops | 提升 |
|---|---|---|---|
| 2K | 1509.98 ms | 1375.95 ms | 8.9% |
| 4K | 2779.46 ms | 2715.18 ms | 2.3% |
| 8K | 5810.53 ms | 5619.48 ms | 3.3% |
LongCat-Flash-Lite-FP8:Router GEMM。
Router GEMM 单独使用 1,024 token 输入和 128 token 输出进行评估。在 batch size 为 1 时,输入吞吐量基本持平,提升了 0.5%,而在 batch size 4–64 范围内则提升了 5.5–6.1%。
表 10:使用 HPC-Ops Router GEMM 的 LongCat-Flash-Lite-FP8 输入吞吐量。越高越好。
| Batch | SGLang 默认 | HPC-Ops Router GEMM | 改进 |
|---|---|---|---|
| 1 | 16,612.11 tok/s | 16,695.77 tok/s | 0.5% |
| 4 | 54,466.27 tok/s | 57,810.27 tok/s | 6.1% |
| 8 | 60,425.93 tok/s | 63,833.96 tok/s | 5.6% |
| 16 | 61,995.23 tok/s | 65,539.10 tok/s | 5.7% |
| 32 | 62,833.85 tok/s | 66,306.52 tok/s | 5.5% |
| 64 | 62,841.93 tok/s | 66,422.92 tok/s | 5.7% |

图 5:SGLang 端到端结果。三个 Hy3-FP8 面板同时启用了 FP8 KV cache、HPC-Ops Attention 和 MoE;右下角面板单独隔离了 Router GEMM。
H200 服务验证
上游 pull request 还在 H200 上评估了 SGLang 服务循环中集成后的算子,在主要调优目标 H20 之外提供了模型级别的集成检查。
表 11:上游 SGLang pull request 中报告的模型级服务验证。
| 算子 | 上游验证工作负载 | 对比 | 结果 |
|---|---|---|---|
| Attention | Hy3-FP8 搭配 FP8 KV cache 的服务工作负载 | HPC-Ops Attention 对比 FlashAttention | 输出吞吐量:+3.7–5.9% |
| Router GEMM | LongCat-Flash Lite prefill 服务工作负载 | HPC-Ops Router GEMM 对比 SGLang 默认实现 | 输入吞吐量:+2.8–5.4% |
| MoE | Qwen3 与 Hy3 FP8 MoE 服务工作负载 | HPC-Ops MoE 对比 SGLang 默认实现 | 输出吞吐量:Qwen3 从持平到 +2.7%;Hy3 −4.2% 至 +6.3% |
上游集成也经过了数值和模型层面的保真度检查。注意力测试在 BF16 和 FP8 下均通过,所评估的 Hy3 FP8 贪心输出与 BF16 路径逐 token 一致。Router GEMM 在与 FP32 参考实现的对比中通过,并保持了贪心输出。对于 Qwen3,HPC-Ops MoE 路径与 Triton 相对于 FP32 的误差相当,余弦相似度为 0.99974,最大相对误差为 0.024。完整配置和逐用例结果可在上游 PR 中查看。
下一步
这项工作是 HPC-Ops 与 SGLang 社区更广泛合作的一部分。我们将继续与 SGLang 维护者和贡献者合作,改进和扩展这些算子,并在更多 HPC-Ops 能力成熟后将其上游化。非常欢迎反馈、问题和基准测试,我们期待共同推进开放、高性能的 LLM 推理。
致谢
我们要感谢各团队中众多共同努力将这些算子引入 SGLang 的人:
- 腾讯混元 AI Infra —— 构建并优化了 HPC-Ops 的 Attention、Router GEMM 和 MoE 算子,并将它们贡献给 SGLang。Sethran Liu、Chase Shao、Shengy Wei、Theo Cheng、Ryann Xue、Lando Jiang、Looper Zhao、Haank Lin、Aiden Ren、Lehua Ding、Chengv Jiang、Steven Kuang、Liqi He、Kipper Gong、Reedlau Liu、Raccoon Liu、Dick Zhu。
- 腾讯网络平台部——感谢在通信优化方面的紧密合作。Xuan Zhang、Haoran Zhao、Yuanyuan Gong、Yadong Liu、Jinzhu Wang、Yinben Xia、Xiang Li、Quan Wen、Zekun He。
- SGLang——感谢开放的后端接口、评审和设计讨论。Xiaoyu Zhang(BBuf)、Xinyuan Tong、Ke Bao,以及整个 SGLang 团队。
- NVIDIA——感谢在 kernel 与性能优化方面的紧密合作。Yuanhang Sun、Perkz Zheng、Yuxi Chi、Jiang Shao、Jun Gu、Meng Wang、River Liu、Gary Ji、Chandler Zhou。
我们还要感谢更广泛的开源 kernel 社区,本工作建立在其成果之上并与之进行对比评测,包括 NVIDIA CUTLASS/CuTe、TensorRT-LLM、FlashInfer、FlashAttention 和 Triton。
HPC-Ops is an open-source operator library for LLM inference, deployed in Tencent's large-scale production serving. Its core operators, including Dynamic Attention and Fused MoE, play a critical role in Hunyuan's online inference, reducing TPOT of Hy3 model by up to 48.8%. HPC-Ops Attention, Router GEMM, and MoE are now integrated into SGLang's main branch, bringing these production-proven optimizations to the open-source serving community.
In this blog, we introduce the design of three important operators in HPC-Ops and their integration with SGLang. We then present operator benchmarks and serving results on H20 together with the H200 validation results. The integrations target NVIDIA Hopper GPUs (SM90) and have been validated with Qwen3, Hy3, and LongCat workloads.
Highlights
- Attention: On H20, HPC-Ops dynamic scheduling reaches 2.95× over its static split-KV schedule and is on average 2.25× faster than the best of FlashInfer and FlashAttention in each measured case. In upstream H200 validation, the integrated Hy3-FP8 path with FP8 KV cache improves output throughput by 3.7–5.9% over FlashAttention.
- Router GEMM: On H20, HPC-Ops is 1.30–3.22× faster than FP32 cuBLAS, while its maximum absolute error relative to FP32 cuBLAS is 0.00177, versus 0.06464 for TF32 cuBLAS. In the upstream H200 LongCat-Flash kernel validation, it delivers a 4.31× speedup over the existing FP32 path.
- MoE: On H20, HPC-Ops delivers mean per-batch speedups of 1.08× at TP8 / EP1 and 1.21× at TP1 / EP8 over the best of the SGLang and vLLM baselines on Hy3. In the upstream Qwen3/H200 kernel benchmark, it reaches up to 4.21× over Triton at eight tokens.
- End-to-end serving: On 8× H20 with Hy3-FP8, enabling HPC-Ops Attention and MoE together reduces TPOT by 15.1–48.8% at batch sizes 4–64 and TTFT by 3.3–6.0% at batch sizes 4–16. On 8× H20 with LongCat-Flash-Lite-FP8, enabling HPC-Ops Router GEMM improves input throughput by 5.5–6.1% at batch sizes 4–64.
Attention, routing, and experts: three hot paths in MoE model serving
Production MoE serving rarely resembles the uniform workloads measured in isolated kernel benchmarks. It combines mixed-length Attention work, precision-sensitive routing, and sparse expert execution within the same latency-sensitive path; long-context, multi-turn, and agentic workloads further widen the distribution of live KV lengths. Serving performance therefore depends not only on raw matrix-multiplication throughput, but also on workload balance, numerical fidelity, and overhead control.
These constraints surface in three performance-critical stages of MoE model serving. During decode, Attention work scales with each request's live KV length, making mixed-length batches a load-balancing problem. Router GEMM produces the scores used for top-k selection, where small numerical changes can alter expert choices. The selected experts then process small and uneven token groups, allowing metadata construction, token movement, intermediate storage, and launch overhead to rival the expert GEMMs themselves.
HPC-Ops addresses each stage with a dedicated operator: workload-aware scheduling for Attention, a precision-aware formulation for Router GEMM, and a fused pipeline for MoE that eliminates the standalone gather and reduces launch and intermediate traffic. The upstream integration pairs these operators with SGLang's serving runtime through its native backend and dispatch interfaces. The following sections explain how each operator is designed.
Attention: load balancing for mixed-length decode
During decode, each new token attends over the request's full KV cache, so Attention work scales with the live sequence length. A request with 16K cached tokens therefore carries roughly 16× the KV work of one with 1K. In production, prompt and output lengths vary widely, and continuous batching places requests at different stages of generation in the same launch; a batch therefore routinely mixes short KV caches with sequences tens of thousands of tokens long.
A static split-KV schedule maps work to a fixed launch grid over KV heads, requests, and KV chunks, with one partitioning policy shared across the batch. A static split-KV scheduler generally follows one of two policies, neither of which performs well for mixed-length batches. (1) Fix the split count, and long requests produce much heavier chunks: short-request CTAs finish early while a few long-running CTAs determine the kernel tail. (2) Fix the chunk size instead, and the grid must reserve enough splits for the longest request, leaving shorter requests with empty or nearly empty chunks that still consume scheduling slots. One policy creates uneven work; the other schedules nonexistent work.
Scheduling around live KV work
HPC-Ops replaces the static per-request split with a persistent kernel that dynamically balances KV tiles across CTAs according to the batch's actual length distribution. For each decode batch, an assign kernel builds a global task map from live KV lengths: it slices every sequence into uniform 64-token tiles, sums the tile count across all heads and requests, and divides the total by the number of persistent CTAs to set a per-CTA tile budget. The assignment kernel fills each CTA's bin up to that budget before spilling into the next, so long sequences span multiple CTAs in proportion to their length while short sequences contribute only the tiles they actually have. A minimum-work floor prevents over-partitioning when total work is small, keeping the downstream combine inexpensive. The task map is generated once per decode step from device-side sequence lengths and reused across Transformer layers, amortizing its cost.
At execution time, each CTA drains its assigned bin. For every descriptor, it computes Attention over one or more contiguous KV tiles and writes a partial output with its log-sum-exp statistic; the same resident CTA continues to the next descriptor until its bin is empty. Because each CTA produces only a subset of the partials for a given request, a final combine kernel reads the actual chunk count per request and head and merges the partials under the correct global softmax normalization. The near-equal bin sizes ensure that CTAs finish at roughly the same time, eliminating the kernel tail that a few unusually long requests would otherwise cause.
A fused attention prologue
For Hy3 FP8, HPC-Ops fuses the Attention prologue after the QKV projection: it applies QK-Norm before RoPE, emits Q in FP8 with a per-token, per-head scale, and writes K and V directly into the paged FP8 cache. It passes the quantized Q and its scale directly to the main Attention kernel, avoiding requantization. The fused path eliminates intermediate tensors and their associated HBM round-trips and separate kernel launches in both prefill and decode.
Router GEMM: balancing routing precision and throughput
Router precision directly affects MoE model quality. At each MoE layer, the router projects hidden states into expert scores, and a top-k selection over these scores determines which experts execute. The score differences between the k-th and (k+1)-th expert can be small, so the arithmetic precision of this projection determines whether the correct experts are selected.
To preserve router precision, some production models retain FP32 router weights even when hidden states are BF16. Casting those weights to BF16 enables BF16 Tensor Core throughput but discards low-order mantissa bits that can flip a top-k decision. A full FP32 GEMM preserves all weight precision, but with lower Tensor Core throughput.
A precision-aware BF16 formulation
HPC-Ops resolves this by decomposing the FP32 weight into two BF16 components. It extracts a BF16 high part by direct truncation, then forms a second BF16 component from the scaled residual . The original weight is approximated as , so the matrix product becomes two BF16 GEMMs whose results are combined with a scale correction to recover the low-order mantissa contribution. A single kernel executes both BF16 multiplications: it loads activation tiles once from shared memory, accumulates both partial results in FP32 registers, applies the scaling in the epilogue, and writes the final FP32 router scores to global memory. This formulation recovers precision close to a full FP32 GEMM while running the main arithmetic on BF16 Tensor Cores.
On the framework side, SGLang caches the decomposed weight pair at model load time and reuses it across requests and CUDA graph replays. A shape-aware dispatch selects between the HPC-Ops kernel and the default path at measured crossover points. Below these points, the single FP32 path is faster because the two-product overhead exceeds the Tensor Core gain.
MoE: reducing overhead around small expert GEMMs
During decode, each expert in an MoE layer receives only a handful of tokens. The resulting expert GEMMs are small and memory-bound, and the GPU's SMs are underutilized at these shapes. The problem is compounded by load imbalance: the number of tokens routed to each expert varies across experts and shifts from step to step, making it difficult to spread these small, uneven tiles evenly across the available SMs.
Beyond the expert GEMMs themselves, the operations surrounding them introduce substantial overhead. A conventional MoE path chains separate kernels for routing, gathering tokens into per-expert buffers, Gate-Up GEMM, activation and quantization, Down GEMM, and top-k weighted reduction back to token positions. The gather step materializes a full token tensor in HBM before any matmul begins, and each subsequent stage pays its own kernel launch and HBM round-trip for intermediates. When the GEMMs are small, this surrounding overhead consumes a comparable fraction of the stage's wall time.
A fused, latency-oriented MoE pipeline
For low-batch-size inference, the HPC-Ops MoE backend coordinates routing and index preprocessing, Gate-Up, activation and requantization, Down, and top-k weighted reduction in a low-latency pipeline built around task-map-driven persistent expert GEMMs.
- Routing and index build. Starting from the selected top-k expert IDs, a shared-memory counting pass organizes token–expert assignments into contiguous per-expert output ranges, reducing global atomic pressure and building the routing indices and per-tile task maps consumed directly by the persistent expert GEMMs.
- Gate-Up and activation. The Gate-Up GEMM reads original tokens directly through the routing indices, skipping the standalone gather and its extra HBM traffic. SiLU-and-mul and FP8 requantization then run as one fused kernel whose output the Down GEMM reads directly.
- Occupancy-first, without warp specialization. A single warp group handles both data movement and matrix math rather than reserving separate producer and consumer groups. This raises CTA residency and shifts memory-latency hiding from an intra-CTA software pipeline to cross-CTA hardware scheduling. Persistent grids then consume these task maps and spread the small, uneven expert tiles across the SMs.
- PDL-chained stages. Programmatic Dependent Launch overlaps each downstream kernel launch with the tail of the preceding stage, reducing gaps across Gate-Up, activation, Down, and the final top-k weighted reduction, which restores expert outputs to token order.
Together, these optimizations reduce intermediate traffic and kernel-launch overhead on the critical path.
From HPC-Ops kernels to SGLang
Through SGLang's native backend and dispatch interfaces, HPC-Ops operates directly on the serving runtime's existing state while remaining an independently maintained operator library. Attention consumes paged KV storage and live device-side sequence metadata without an additional layout conversion; Router GEMM reuses preprocessed weights and workspace across requests and CUDA graph replays; and MoE follows SGLang's expert IDs and partitions without additional remapping. These integrations preserve each operator's intended data path while fitting SGLang's existing execution model.
The three integrated operator paths are summarized below:
| HPC-Ops operator | What it optimizes | Precision | Upstream PRs |
|---|---|---|---|
| Attention | Load-balanced mixed-length decode and a fused QK-Norm, RoPE, quantization, and KV-write prologue | BF16 activations; BF16 or FP8 E4M3 KV cache | #30540, #32304 |
| Router GEMM | Precision-aware router projection using BF16 Tensor Cores while retaining FP32 weight information | BF16 activations × FP32 weights → FP32 scores | #30247, #31943 |
| MoE | Low-overhead execution around small and uneven expert GEMMs | BF16 hidden states; FP8 E4M3 expert weights | #30541 |
Getting started
This guide describes how to use the HPC-Ops Attention, Router GEMM, and MoE operators in SGLang.
Install
To install HPC-Ops from source:
git clone https://github.com/Tencent/hpc-ops.git
cd hpc-ops
make wheel
python3 -m pip install dist/*.whl
HPC-Ops is already included in SGLang's official x86_64 development images (lmsysorg/sglang:dev, or lmsysorg/sglang:dev-cu12 for CUDA 12.9), so no separate installation is required when using these images.
Attention and MoE
Attention and MoE are independent backend choices in SGLang and can be enabled separately or together for compatible models such as Qwen3 and Hy3. The following example selects both HPC-Ops backends and enables the FP8 KV-cache Attention path:
python3 -m sglang.launch_server \
--model tencent/Hy3-FP8 \
--tp-size 8 \
--attention-backend hpc_ops \
--kv-cache-dtype fp8_e4m3 \
--page-size 64 \
--moe-runner-backend hpc_ops
For BF16 KV cache, omit --kv-cache-dtype fp8_e4m3. To use only one HPC-Ops operator, specify only the corresponding backend option.
Router GEMM
In SGLang, HPC-Ops Router GEMM retains low-order information from FP32 router weights while executing the matrix math on BF16 Tensor Cores. The integrated path has been validated on LongCat-Flash Chat and Lite and is selected automatically for supported model and router shapes. Once HPC-Ops is installed, a standard LongCat-Flash launch can use it:
python3 -m sglang.launch_server \
--model meituan-longcat/LongCat-Flash-Lite-FP8
Performance evaluation
The HPC-Ops backends currently support NVIDIA Hopper-architecture GPUs and deliver their best performance on H20. The evaluation below covers operator benchmarks on H20, end-to-end SGLang serving on 8× H20, and the H200 results reported in the upstream SGLang pull requests.
H20 operator benchmarks
Attention.
The Attention scheduler's headline benefit appears in mixed-length decode, where requests in the same batch can have very different KV-cache lengths. We evaluate FP8 KV-cache decode from uniform to highly skewed distributions; in the table, A×B denotes A requests with KV length B. To isolate the scheduling effect, we compare HPC-Ops dynamic scheduling with its static split-KV counterpart, while FlashInfer and FlashAttention provide additional baselines. The dynamic-vs-static gain grows with skew, from parity on the uniform 64×0.5K batch to 2.95× on the 1×128K + 31×4K mix. Across all six cases, dynamic scheduling is on average 2.25× faster than the best of FlashInfer and FlashAttention in each case.
Table 1: Decode latency across KV-length distributions on H20. Lower is better.
| Decode scenario | HPC-Ops dynamic | HPC-Ops static | FlashInfer | FlashAttention | Dynamic vs. static |
|---|---|---|---|---|---|
| 64×0.5K | 0.013 ms | 0.013 ms | 0.050 ms | 0.025 ms | 1.00× |
| 64×4K | 0.033 ms | 0.043 ms | 0.221 ms | 0.095 ms | 1.32× |
| 32×0.125K + 32×4K | 0.020 ms | 0.033 ms | 0.119 ms | 0.053 ms | 1.59× |
| 2×32K + 30×4K | 0.032 ms | 0.056 ms | 0.169 ms | 0.094 ms | 1.76× |
| 1×64K + 15×4K | 0.042 ms | 0.097 ms | 0.118 ms | 0.065 ms | 2.32× |
| 1×128K + 31×4K | 0.063 ms | 0.186 ms | 0.220 ms | 0.097 ms | 2.95× |

Figure 1: Dynamic scheduling becomes increasingly effective as live KV work grows more skewed. Lower is better.
Router GEMM.
We evaluate Router GEMM first with a generic sweep. Across the measured M values, HPC-Ops is 1.30–3.22× faster than FP32 cuBLAS and 1.25–1.78× faster than TF32 cuBLAS. Using FP32 cuBLAS as the numerical reference, the maximum absolute error remains at or below 0.00177, compared with 0.06464 for TF32.
Table 2: BF16 × FP32 Router GEMM latency at K = 4096, N = 192 on H20. Lower is better.
| M | HPC-Ops | FP32 cuBLAS | TF32 cuBLAS | Speedup vs. FP32 | Speedup vs. TF32 |
|---|---|---|---|---|---|
| 1 | 11.200 µs | 14.576 µs | 14.048 µs | 1.30× | 1.25× |
| 16 | 11.744 µs | 23.808 µs | 18.752 µs | 2.03× | 1.60× |
| 48 | 12.144 µs | 31.008 µs | 20.064 µs | 2.55× | 1.65× |
| 96 | 13.904 µs | 31.760 µs | 24.720 µs | 2.28× | 1.78× |
| 208 | 17.088 µs | 39.280 µs | 28.928 µs | 2.30× | 1.69× |
| 512 | 26.992 µs | 86.976 µs | 44.736 µs | 3.22× | 1.66× |
| 1024 | 50.640 µs | 110.480 µs | 68.544 µs | 2.18× | 1.35× |
| 2048 | 76.688 µs | 198.576 µs | 100.800 µs | 2.59× | 1.31× |
| 4096 | 141.120 µs | 403.728 µs | 205.760 µs | 2.86× | 1.46× |

Figure 2: Router GEMM numerical error relative to FP32 cuBLAS (left) and latency versus FP32 and TF32 cuBLAS (right). Lower is better.
We then retest the two router shapes used by LongCat-Flash. Within SGLang's model-aware dispatch ranges, HPC-Ops delivers 1.06–2.83× speedup for the Chat shape and 1.09–2.46× for the Lite shape over the SGLang default.
Table 3: LongCat-Flash Router GEMM latency over the SGLang dispatch ranges on H20. Lower is better.
| M | Chat default | Chat HPC-Ops | Speedup | Lite default | Lite HPC-Ops | Speedup |
|---|---|---|---|---|---|---|
| 64 | 39.19 µs | 37.01 µs | 1.06× | — | — | — |
| 128 | 74.18 µs | 59.36 µs | 1.25× | 25.83 µs | 23.72 µs | 1.09× |
| 256 | 100.03 µs | 82.47 µs | 1.21× | 41.87 µs | 34.01 µs | 1.23× |
| 512 | 190.37 µs | 141.73 µs | 1.34× | 71.89 µs | 41.95 µs | 1.71× |
| 1024 | 380.68 µs | 207.00 µs | 1.84× | 108.64 µs | 74.09 µs | 1.47× |
| 2048 | 961.15 µs | 339.04 µs | 2.83× | 235.81 µs | 106.81 µs | 2.21× |
| 4096 | 1469.70 µs | 670.14 µs | 2.19× | 423.52 µs | 172.44 µs | 2.46× |
| 8192 | 2881.00 µs | 1333.84 µs | 2.16× | 835.22 µs | 339.66 µs | 2.46× |

Figure 3: Router GEMM latency on the LongCat-Flash Chat (left) and Lite (right) shapes over SGLang's dispatch ranges. Lower is better.
MoE.
For MoE, we benchmark the full fused operation under Hy3 shapes at TP8 / EP1 and TP1 / EP8 against SGLang, vLLM Triton, and vLLM CUTLASS. Taking the lowest latency among the three baselines in each row, HPC-Ops delivers a mean per-batch speedup of 1.08× at TP8 / EP1 and 1.21× at TP1 / EP8, with the largest gains at the small-to-mid batch sizes common in low-latency decode.
Table 4: Hy3 MoE latency at TP8 / EP1 on H20. Lower is better.
| Batch | HPC-Ops | SGLang | vLLM Triton | vLLM CUTLASS | Speedup vs. best |
|---|---|---|---|---|---|
| 16 | 85.7 µs | 88.6 µs | 124.2 µs | 209.2 µs | 1.03× |
| 32 | 124.0 µs | 137.2 µs | 184.3 µs | 275.6 µs | 1.11× |
| 64 | 147.2 µs | 164.4 µs | 374.9 µs | 330.3 µs | 1.12× |
| 128 | 161.5 µs | 179.9 µs | 302.9 µs | 345.3 µs | 1.11× |
| 256 | 170.1 µs | 191.5 µs | 310.9 µs | 351.6 µs | 1.13× |
| 512 | 194.5 µs | 230.1 µs | 331.6 µs | 369.2 µs | 1.18× |
| 1024 | 281.4 µs | 300.5 µs | 652.7 µs | 438.3 µs | 1.07× |
| 2048 | 491.8 µs | 522.5 µs | 731.5 µs | 794.4 µs | 1.06× |
| 4096 | 872.0 µs | 899.2 µs | 1366.0 µs | 1230.7 µs | 1.03× |
| 8192 | 1695.0 µs | 1712.7 µs | 2216.8 µs | 2362.9 µs | 1.01× |
| 16384 | 3241.9 µs | 3257.1 µs | 4329.1 µs | 4364.4 µs | 1.00× |
Table 5: Hy3 MoE latency at TP1 / EP8 on H20. Lower is better.
| Batch | HPC-Ops | SGLang | vLLM Triton | vLLM CUTLASS | Speedup vs. best |
|---|---|---|---|---|---|
| 4 | 118.6 µs | 183.1 µs | 147.4 µs | 140.4 µs | 1.18× |
| 8 | 136.7 µs | 231.5 µs | 192.8 µs | 170.7 µs | 1.25× |
| 16 | 149.8 µs | 234.2 µs | 198.4 µs | 263.5 µs | 1.32× |
| 32 | 153.6 µs | 475.3 µs | 214.6 µs | 264.4 µs | 1.40× |
| 64 | 166.5 µs | 477.3 µs | 358.1 µs | 266.8 µs | 1.60× |
| 128 | 213.5 µs | 482.3 µs | 251.7 µs | 272.6 µs | 1.18× |
| 256 | 386.2 µs | 494.3 µs | 454.9 µs | 493.5 µs | 1.18× |
| 512 | 705.5 µs | 970.7 µs | 691.7 µs | 741.7 µs | 0.98× |
| 1024 | 1342.6 µs | 1476.8 µs | 1369.1 µs | 1359.1 µs | 1.01× |
| 2048 | 2513.9 µs | 2871.2 µs | 2668.7 µs | 2530.4 µs | 1.01× |

Figure 4: Hy3 MoE latency across TP8 / EP1 and TP1 / EP8 configurations. Lower is better.
H200 operator validation
The upstream PRs also include H200 serving results, confirming that the performance gains generalize across Hopper GPUs.
Table 6: Operator validation reported in the upstream SGLang pull requests.
| Operator | Upstream validation workload | Comparison | Result |
|---|---|---|---|
| FP8 Attention | Hy3-FP8 with FP8 KV cache; mixed-length decode | HPC-Ops dynamic scheduling vs. HPC-Ops static split-KV | Output throughput +2.0%; total throughput +2.0%; median TTFT −5.3% |
| BF16 Attention | Qwen3 with BF16 KV cache; mixed-length decode | HPC-Ops dynamic scheduling vs. HPC-Ops static split-KV | Output throughput +3.0%; mean E2E latency −2.8%; mean TPOT −2.8% |
| Router GEMM | LongCat-Flash Chat and Lite router shapes | HPC-Ops Router GEMM vs. SGLang default | Kernel speedup: 1.56–4.31× |
| MoE | Qwen3 FP8 MoE workloads from 1 to 4,096 tokens | HPC-Ops MoE vs. SGLang Triton fused experts | Kernel speedup: 0.89–4.21× |
End-to-end performance
The end-to-end evaluation runs on 8× NVIDIA H20 GPUs against the corresponding default SGLang implementations. On Hy3-FP8 at TP8 with FP8 KV cache, we measure the combined serving impact by enabling HPC-Ops Attention and MoE together. On LongCat-Flash-Lite-FP8, only Router GEMM is measured. We also summarize the H200 serving validation reported in the upstream SGLang pull requests.
Hy3-FP8: Attention and MoE.
With an 8K input and 4K output, HPC-Ops reduces TPOT by 3.3% at batch size 1. Across batch sizes 4–64, the reduction grows to 15.1–48.8%.
Table 7: Hy3-FP8 TPOT with FP8 KV cache and HPC-Ops Attention and MoE enabled together. Lower is better.
| Batch | SGLang default | HPC-Ops | Improvement |
|---|---|---|---|
| 1 | 7.56 ms | 7.31 ms | 3.3% |
| 4 | 11.10 ms | 9.42 ms | 15.1% |
| 8 | 14.29 ms | 10.76 ms | 24.7% |
| 16 | 22.90 ms | 13.09 ms | 42.8% |
| 32 | 35.33 ms | 18.09 ms | 48.8% |
| 64 | 40.70 ms | 23.81 ms | 41.5% |
With an 8K input, HPC-Ops improves TTFT by 3.3–9.0% across batch sizes 1–16.
Table 8: Hy3-FP8 TTFT with FP8 KV cache for an 8K input. Positive improvements mean lower latency.
| Batch | SGLang default | HPC-Ops | Improvement |
|---|---|---|---|
| 1 | 460.67 ms | 419.43 ms | 9.0% |
| 4 | 1612.47 ms | 1533.66 ms | 4.9% |
| 8 | 3210.93 ms | 3018.68 ms | 6.0% |
| 16 | 5810.53 ms | 5619.48 ms | 3.3% |
At batch size 16, we also sweep the input length from 2K to 8K with chunked prefill and prefix caching disabled. HPC-Ops improves TTFT by 2.3–8.9% across the three input lengths.
Table 9: Hy3-FP8 TTFT with FP8 KV cache across input lengths at batch size 16. Positive improvements mean lower latency.
| Input length | SGLang default | HPC-Ops | Improvement |
|---|---|---|---|
| 2K | 1509.98 ms | 1375.95 ms | 8.9% |
| 4K | 2779.46 ms | 2715.18 ms | 2.3% |
| 8K | 5810.53 ms | 5619.48 ms | 3.3% |
LongCat-Flash-Lite-FP8: Router GEMM.
Router GEMM is evaluated separately with a 1,024-token input and a 128-token output. Input throughput remains near parity at batch size 1, with a 0.5% improvement, and improves by 5.5–6.1% across batch sizes 4–64.
Table 10: LongCat-Flash-Lite-FP8 input throughput with HPC-Ops Router GEMM. Higher is better.
| Batch | SGLang default | HPC-Ops Router GEMM | Improvement |
|---|---|---|---|
| 1 | 16,612.11 tok/s | 16,695.77 tok/s | 0.5% |
| 4 | 54,466.27 tok/s | 57,810.27 tok/s | 6.1% |
| 8 | 60,425.93 tok/s | 63,833.96 tok/s | 5.6% |
| 16 | 61,995.23 tok/s | 65,539.10 tok/s | 5.7% |
| 32 | 62,833.85 tok/s | 66,306.52 tok/s | 5.5% |
| 64 | 62,841.93 tok/s | 66,422.92 tok/s | 5.7% |

Figure 5: End-to-end SGLang results. The three Hy3-FP8 panels use FP8 KV cache with HPC-Ops Attention and MoE enabled together; the bottom-right panel isolates Router GEMM.
H200 serving validation
The upstream pull requests also evaluated the integrated operators in the SGLang serving loop on H200, providing a model-level integration check beyond the primary H20 tuning target.
Table 11: Model-level serving validation reported in the upstream SGLang pull requests.
| Operator | Upstream validation workload | Comparison | Result |
|---|---|---|---|
| Attention | Hy3-FP8 with FP8 KV cache serving workloads | HPC-Ops Attention vs. FlashAttention | Output throughput: +3.7–5.9% |
| Router GEMM | LongCat-Flash Lite prefill serving workloads | HPC-Ops Router GEMM vs. SGLang default | Input throughput: +2.8–5.4% |
| MoE | Qwen3 and Hy3 FP8 MoE serving workloads | HPC-Ops MoE vs. SGLang default | Output throughput: Qwen3 from parity to +2.7%; Hy3 −4.2% to +6.3% |
The upstream integrations were also checked for numerical and model-level fidelity. Attention tests passed across BF16 and FP8, and the evaluated Hy3 FP8 greedy outputs matched the BF16 path token for token. Router GEMM passed comparisons against the FP32 reference and preserved greedy outputs. For Qwen3, the HPC-Ops MoE path matched Triton's error against FP32, with a cosine similarity of 0.99974 and a maximum relative error of 0.024. Full configurations and per-case results are available in the upstream PRs.
What's next
This work is part of a broader collaboration between HPC-Ops and the SGLang community. We will continue working with SGLang maintainers and contributors to improve and extend these operators and upstream additional HPC-Ops capabilities as they mature. Feedback, issues, and benchmarks are very welcome, and we look forward to advancing open, high-performance LLM inference together.
Acknowledgments
We would like to thank the many people across teams who worked together to bring these operators to SGLang:
- Tencent Hunyuan AI Infra — for building and optimizing the HPC-Ops Attention, Router GEMM, and MoE operators and contributing them to SGLang. Sethran Liu, Chase Shao, Shengy Wei, Theo Cheng, Ryann Xue, Lando Jiang, Looper Zhao, Haank Lin, Aiden Ren, Lehua Ding, Chengv Jiang, Steven Kuang, Liqi He, Kipper Gong, Reedlau Liu, Raccoon Liu, Dick Zhu.
- Tencent Network Platform Department — for the close collaboration on communication optimization. Xuan Zhang, Haoran Zhao, Yuanyuan Gong, Yadong Liu, Jinzhu Wang, Yinben Xia, Xiang Li, Quan Wen, Zekun He.
- SGLang — for the open backend interfaces, reviews, and design discussions. Xiaoyu Zhang (BBuf), Xinyuan Tong, Ke Bao, and the entire SGLang team.
- NVIDIA — for the close collaboration on kernel and performance optimization. Yuanhang Sun, Perkz Zheng, Yuxi Chi, Jiang Shao, Jun Gu, Meng Wang, River Liu, Gary Ji, Chandler Zhou.
We also thank the broader open-source kernel community whose work this builds on and measures against, including NVIDIA CUTLASS/CuTe, TensorRT-LLM, FlashInfer, FlashAttention, and Triton.